As individual transistors within integrated circuits are scaled to smaller and smaller dimensions, engineering refinements in transistor design are necessary to maintain optimum device performance. Typically, in metal-oxide-semiconductor (MOS) devices having channel lengths in the submicron range, the drain regions must be carefully fabricated to avoid performance degradation arising from hot carrier injection, drain leakage, punch-through, and the like. Where the transistor channel length is near one micron, many device performance problems can be corrected by forming a lightly-doped-drain (LDD) region. The LDD region lowers the electric field in the channel region of the transistor in the immediate vicinity of the drain region. The reduced electric field in the channel region improves the threshold voltage stability of the transistor by reducing hot carrier injection into the gate oxide layer overlying the channel region. However, when the channel length of the transistor is reduced to dimensions near 0.5 microns and below, drain engineering techniques, such as LDD and the like, fail to prevent performance degradation.
Additionally, counter doped source-drain regions have been used to reduce subsurface punch-through in short channel devices. In the case of an n-channel device, a boron "halo" is formed around the n-type source and drain regions. Although the halo is effective in reducing punch-through, the drive current of the transistor is also reduced leading to poor performance. To further reduce the impact of device performance degradation arising from short channel effects, transistors have been designed to operate at supply voltages of less than 5 volts. However, submicron devices operating at supply voltages of 3 volts continue to exhibit poor device performance even when drain engineering techniques are applied.
Recent development effort in submicron device design has been directed toward engineering the doping junction profiles within the channel region itself. MOS devices having a non-uniformly doped channel can be obtained by providing precisely tailored doping concentration gradients within the channel region of the transistor. To form symmetrical doped regions within the channel region requires that they be precisely defined within the channel region to avoid any asymmetry in the doping concentration profile within the channel region. Channel doping techniques which rely on the critical alignment of photolithographic layers can result in asymmetrical doping profiles if the lithographic alignment does not meet required alignment tolerances. Accordingly, further process development is necessary to provide an MOS device having non-uniform channel doping that can be reliably manufactured, and to provide completely symmetrical doping profiles in submicron transistors.